In computer memory, such as dynamic random-access memory (DRAM), delay lines are used to ensure proper timing in data paths. Each delay line generally implements a coarse delay stage and a fine delay stage. Generally, mismatches between the coarse delay stages are a major source of non-monotonic behavior in timing signals.
Traditional computer memory delay lines use capacitive load switching to produce a fine delay that is independent of the coarse delay. The coarse delay is uncorrelated to the fine delay. A result of using the traditional delay line is non-monotonicity.
It would be desirable to implement a monotonic variable delay line.